The expectations for video quality continue to rise as more applications take advantage of video sources. Transmitting more video data at higher rates requires attention to a range of signal integrity issues summarized here.
Current solutions such as Camera Link, GigE Vision, and other LVDS interfaces have served the industrial market quite well, but are now encountering obstacles associated with reliably transmitting higher-speed data over long cable lengths. Increased EMI often accompanies higher switching data rates. Also, there is the constant desire to minimize both system cost and design complexity.
The following discussion will examine the design challenges associated with moving to higher data rate embedded video interfaces and present several solutions.
CHALLENGES IN COMMON INDUSTRIAL VIDEO APPLICATIONS
Let’s start by looking at a few common applications. Machine vision systems require the transfer of captured image data from a digital camera to a remote frame grabber. The rate of data transfer is influenced by the resolution, bit depth, and frame rate of the image capture. Higher-resolution and bit-depth images are designed to provide the detail required for complex analysis. This is critical for uses such as electronics inspection equipment, where the geometries are shrinking and necessitating more detailed examination. Faster frame rates are desirable to improve overall inspection throughput.
Today’s machine vision systems typically employ the communication interface specified by the Camera Link standard. Published in October 2000, this standard has successfully supported the vision industry for years. The interface consists of parallel differential pairs of serialized data (7:1 ratio), as well as a parallel differential clock. Figure 1 illustrates a common Camera Link interface.
The 7:1 serialization scheme over LVDS provides efficient, robust communication for many applications. However, there are some limitations and challenges when scaling the technology to higher throughput and longer distances. The parallel nature of the differential clock and data pairs (diagrammed in Figure 2) is susceptible to excessive pair-to-pair cable skew when the clock rate and distance increase. Because a separate clock channel is used to sample data at the Camera Link receiver, it is important to maintain the proper setup and hold relationship between the two. As the interconnect length increases, the inter-pair skew increases, possibly exceeding the margin. High-grade and more expensive cable and connector solutions might be required to minimize the skew.
Similar challenges face industrial display systems, where the link is between an image source (an imager or graphic controller) and a digital display. As with vision systems, there is a drive to increase data rates and support higher color depth up to true color at 24 bits per pixel. More significant is the move to HD resolution and beyond, providing useful detail for surveillance and medical applications. Parallel LVDS solutions similar to those used by Camera Link experience the same type of cable skew limitations. As the data rates increase, skew margin is further reduced and maximum cable length decreases.
Using an embedded clock interface eliminates this inter-pair skew limitation. All data and clock are encoded and serialized for transmission over a single differential pair such as shown in Figure 3. The deserializer receives the serial stream and uses a clock and data recovery circuit to extract the clock and data signals.
In addition to removing skew concerns, a serialized solution provides several other advantages. Driving only one differential pair reduces the overall size of the interconnect media. This means smaller cables and connectors can be used, minimizing connector footprint area on the PCB and allowing a narrower and more flexible interface. Reducing the number of pairs in the cable assembly and removing the restriction for tight skew tolerance enables the use of lower-cost cables.
Moving to a serialized interface can have a positive impact on system design. However, some considerations must be addressed when designing with an embedded clock scheme. First, designers must consider the fact that the data rate on the differential pair is now much higher. Data that was once transmitted over four pairs is now sent on only one pair – approximately a 4x increase in data rate.
TECHNIQUES THAT EASE DESIGN
Other design considerations are associated with higher interface speeds, along with the array of features and techniques available to ease design and enable robust and cost-effective solutions.
At these higher data rates, signal integrity becomes more critical. Designers are no longer concerned with the alignment of clock and data, but rather with the eye opening of each bit within the serialized data stream. As data traverses the cable, the signal is degraded due to the effects of attenuation, jitter, and Inter-Symbol Interference (ISI). To be received correctly, it is important that the data eye be open at the end of the cable – the input to the deserializer.
Cable equalization and de-emphasis are two features targeted at combating signal degradation. The effect of equalization is to reopen the differential signal’s data eye at the far end of a cable, as illustrated in Figure 4. An equalizer applies a high-pass filter and gain curve that is inversely proportional to the cable’s attenuation curve. The ability to program the equalizer’s gain allows for tuning to optimize performance with different cables and lengths. This circuit can be discrete or built in to the deserializer’s input.
The second technique, signal de-emphasis, combats the effects of ISI. Depending on the data pattern being transmitted, a charge might build up on the cable. This impedes the ability to quickly switch to the opposite state. ISI results in the loss of signal amplitude and is especially apparent when sending a single bit, for example, a single one in the midst of a long string of zeros. The energy of this single-bit transition is not enough to offset the charge stored in the cable, thus a closed eye appears at the deserializer’s input.
De-emphasis (with effects shown in Figure 5) reduces the output voltage driven on the line after the initial transition is complete. This minimizes charge buildup on the cable and the associated DC offset and allows the signal to easily transition to a new state. The level of de-emphasis should be adjustable such that the effect can be optimized for interconnect characteristics.
EMI: A UNIVERSAL ISSUE
A challenge common to all systems, whether using a traditional or serialized interface, is EMI reduction. As resolutions and color depths increase, the edge rate and number of channels switching increases, resulting in increased emissions. This can be attacked on several fronts, starting with LVDS and its widespread use. LVDS has a common parallel video interface (four data pairs and one clock pair) and is used in serialized embedded clock solutions.
However, the connection to the source and sink devices (frame grabber or display) might use an LVCMOS interface. Wide parallel LVCMOS output buses are notorious as emissions hot spots. It is important to try to minimize the energy related to these outputs switching and to spread the spectrum of this energy where possible. As parallel outputs switch faster, the edge rates need to increase. Output transitions should be as slow as practical to support the required switching frequency and output loading. Deserializers with programmable output drive provide this flexibility.
Spreading the spectrum of energy is a common practice to reduce peak emissions. In some cases, a source might provide a spread-spectrum clock. The selected serializer and deserializer should be capable of tracking this clock modulation to gain the most benefit. Spreading at the source might not always be supported, so it is desirable to use a deserializer that can generate its own spread-spectrum output, targeting emission reduction at the output hot spot.
Even when using chipsets with EMI reduction features, it is critical to follow sound PCB design practices.
A SOLUTION FOR SERIALIZED VIDEO
National Semiconductor’s Channel Link II family of SERDES chipsets is designed to simplify the implementation of serialized video interfaces. A maximum clock frequency of 75 MHz enables HD 720-pixel video. Up to 24 bits of data, accompanying video synchronization signals, and video pixel clock are serialized to a single low-voltage differential output.
The chipsets provide adjustable de-emphasis and equalization for signal conditioning. A proprietary DC balanced encoding scheme, along with data randomization and scrambling, minimizes ISI and reduces emissions on the link, spreading the spectral content that would otherwise be present with a repetitive pattern. Both serializer and deserializer are designed to take advantage of spread-spectrum clocking from an upstream device, as well as provide a self-generated spread-spectrum clock. Additional EMI reduction features include reduced drive strength and staggered switching of parallel output drivers. All parts offer an auto-sleep power-reduction feature, shifting into a low-power mode when input interfaces are inactive.
Parallel bus connections with LVCMOS or LVDS (four data plus one clock) are available. This LVDS interface is equivalent to National’s 28-bit Channel Link product and provides an easy-to-use upgrade path where image source, frame grabber, or display controller include integrated LVDS.
For systems that require higher bandwidth and longer cable drive (compared in Figure 6), National’s FPGA Link solution is an ideal fit. Coupled with cost-effective FPGAs at the sink and source, data rates up to 3.125 Gbps can be achieved over 30 m of cable. The deserializer features a re-timed serial output to drive daisy-chained sinks, which is especially useful in tiled display applications.
Embedded video systems can realize advantages in both performance and cost through the use of a serialized interface. Solid design practices and techniques are important for successful implementation. National’s Channel Link II and FPGA-Link chipsets provide a serialized interface with signal conditioning to minimize skew concerns and allow the use of longer and narrower cables. EMI-reduction features and compatibility with various source and sink devices offer easy-to-use and robust solutions.